1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a dynamic type semiconductor memory device (hereinafter referred to as a "DRAM") having a hierarchical data line structure.
2. Description of the Background Art
FIG. 11 is a block diagram showing an example of a general DRAM structure.
Referring to the figure, in a DRAM 200, a plurality of word lines WL and a plurality of bit line pairs BL (one each is shown in the figure) are arranged crossing each other in a memory cell array 201, and at each crossing between the word line and each bit line of the bit line pair, a memory cell is provided. Based on a row address signal input to row address buffer 202, a row decoder 203 is driven, and one word line is selected. Based on a column address signal input to column address buffer 204, a column decoder 205 is driven, and one bit line pair is selected. A memory cell at a crossing between the thus selected one word line and one of the bit lines of the selected bit line pair is selected. Data is written to the selected memory cell, or data stored in the memory cell is read. Designation of writing/reading of data is performed by a read/write control signal (R/W) applied to a control circuit 208. At the time of data writing, input data (Din) is input to a memory cell which is selected through an I/O circuit 207. Meanwhile, in data reading, data which has been stored in the selected memory cell is detected and amplified by a sense amplifier 206, and externally output as output data (Dout) through I/O circuit 207.
FIG. 12 shows a portion of two sets of bit line pairs of a conventional DRAM, and circuit structure of one bit line pair only is given in detail.
Referring to the figure, a plurality of word lines WL are arranged crossing bit line pair BLa, BLb, and at a crossing between each bit line BLa or BLb and each word line WL, a memory cell MC is provided. In the figure, only one memory cell MCa connected to bit line BLa and one memory cell MCb connected to bit line BLb are shown, and other memory cells are omitted. Each memory cell MC includes a transfer transistor Qs and a memory capacitor C. Transistor Qs is connected between bit line BLa or BLb and memory capacitor C, with its gate connected to word line WL.
To the bit lines BLa and BLb, an N type sense amplifier NSA and a P type sense amplifier PSA are connected. N type sense amplifier NSA includes N channel MOS transistors Q1 and Q2. Transistor Q1 is connected between bit line BLb and a node N1, with its gate connected to bit line BLa. Transistors Q2 is connected between bit line BLa and node N1, with its gate connected to bit line BLb. Node N1 is coupled to a ground potential through an N channel MOS transistor Q3, and a sense amplifier activating signal .phi.SN is applied to the gate of transistor Q3. P type sense amplifier PSA includes P channel MOS transistors Q4 and Q5. Transistor Q4 is connected between bit line BLb and a node N2, with its gate connected to bit line BLa. Transistor Q5 is connected between bit line BLa and node N2, with its gate connected to bit line BLb. Node N2 is connected to a power supply potential Vcc through a P channel MOS transistor Q6, and a sense amplifier activating signal .phi.SP is applied to the gate of transistor Q6. Further, an N channel MOS transistor Q7 is connected between bit line pair BLa and BLb, and an equalizing signal BLEQ is applied to the gate thereof.
Reading operation by the circuit shown in FIG. 12 will be described with reference to a timing chart of FIG. 13.
When a low active row address strobe signal RAS (hereinafter referred to as "RAS") is at the "H" level, that is, in an off time period, sense amplifier activating signal .phi.SN attains to the "H" level, sense amplifier activating signal .phi.SP attains to the "L" level, and sense amplifiers NSA and PSA are active. Therefore, potential of one of the bit line pair BLa and BLb is kept at "H" level, and the potential of the other one is kept at the "L" level.
When row address strobe signal RAS is at the "L" level, that is, in an active period, first, sense amplifier activating signal .phi.SN is set to the "L" level, and sense amplifier activating signal .phi.SP is set to the "H" level. Thus sense amplifiers NSA and PSA are set to an inactive state, and then equalizing signal BLEQ is once set to the "H" level, so that bit line pair BLa and BLb are short-circuited. Consequently, the potentials of bit lines BLa and BLb both attain to an intermediate potential, that is, "precharge potential", which is intermediate between the "H" level and "L" level. Equalizing signal BLEQ is returned to the "L" level, and then a word line driving signal .phi.WL rises to the "H" level. Accordingly, information of a memory cell MC connected to the selected word line WL is read to the corresponding bit line BLa or BLb, and the potential of bit line BLa or BLb slightly rises or falls in accordance with the information of the memory cell MC. At this time, the potential of the bit line BLa or BLb to which the selected memory cell MC is not connected, is kept at the aforementioned precharge potential. Thereafter, sense amplifier activating signal .phi.SN is set to the "H" level , sense amplifier activating signal .phi.SP is set to the "L" level, and sense amplifiers NSA and PSA are activated, whereby potential difference between bit lines BLa and BLb is amplified. As a result, one of the pair of bit lines BLa and BLb having higher potential is fixed at the "H" level, and one having lower potential is fixed at the "L" level. At this state, column decoder 205 is driven, turning on N channel MOS transistors Q7 and Q8 provided between a desired bit line and input/output lines I/Oa and I/Ob. Consequently, potential difference between the desired bit line pair is taken out through one pair of input/output lines I/Oa and I/Ob connected to I/O circuit 207, and thus reading operation is performed.
Thereafter, when row address strobe signal RAS rises to the "H" level, the active period terminates, and word line driving signal .phi.WL falls to the "L" level. Consequently, transistor Qs of the memory cell MC connected to the selected word line WL turns off. However, sense amplifiers NSA and PSA are held at the active state until the start of the next active period. When row address strobe signal RAS attains to the "L" level, starting the active period, the aforementioned operation is again performed.
Writing operation is performed in the manner reverse to the reading operation. Specifically, when write data is applied to I/O circuit 207, one of the input/output lines I/Oa and I/Ob attains to the "H" level, and the potential of the other attains to the "L" level. At this state, column decoder 205 is driven, turning on transistors Q7 and Q8 connected to the desired bit line pair. Consequently, the potentials of input/output lines I/Oa and I/Ob are transmitted to the desired bit line pair, so that one bit line is set to the "H" level and the other bit line is set to the "L" level. At this time, when the potentials appearing on the bit line pair are reversed, sense amplifiers are inverted forcefully, so that each of the bit lines are kept at the desired potential. Meanwhile, by driving the row decoder, one word line is selected, a transistor Qs of the memory cell positioned at the crossing of the word line and the bit line is turned on, and thus the capacitor C and the corresponding bit line are conducted. In this manner, the potential appearing on a desired bit line is kept in a memory cell MC determined by the selection of a desired word line, and thus writing operation is performed.
FIG. 14 shows a structure of a DRAM in which memory array 201 of FIG. 11 is divided into a plurality of sub memory arrays and which includes hierarchical data lines.
Referring to the figure, twelve sub memory arrays 201a-1 to 201d-3 are shown in the figure, arranged in a matrix. A row decoder 203a is provided corresponding to memory arrays 201a-1 to 201a-3, and similarly, row decoders 203b to 203d are provided on the left end of the blocks of respective corresponding sub memory arrays. In a space along the longitudinal direction of each of the sub memory arrays, segment data line pairs SI/Oa and SI/Ob are arranged connected to the bit line pair BLa and BLb provided in the sub memory array, and in a space along the lateral direction of each of the sub memory arrays, global data line pairs GI/Oa and GI/Ob are arranged, to which segment data lines are connected. At end portions of global data line pairs GI/Oa and GI/Ob, preamplifiers PA1 to
are connected.
The operation of the DRAM will be briefly described. As the row decoder is driven, a word line WL of each sub memory array is selected, and the data read from the bit line pair BLa and BLb is read to segment data line pair SI/Oa and SI/Ob. The data read to the segment data line pair is further transferred to the global data line pair GI/Oa and GI/Ob, amplified in preamplifier PA1 and externally output as memory information.
Meanwhile, in the writing operation, data taken from the outside is transferred to the bit line pair of the sub memory array through global data line pair GI/Oa and GI/Ob and segment data line pair SI/Oa and SI/Ob, a desired word line WL is selected by the row decoder, and thus the data is written to a desired memory cell.
As the storage capacity of the memory cell is increased, hierarchical data line structure has been proposed for dissipating capacitance of data lines, in order to external input/output of data on the data lines at high speed, with the memory array divided into a plurality of sub memory arrays.
FIGS. 15 and 16 show conventionally proposed hierarchical data line structures disclosed in ISSCC 91 Digest of Technical Papers pp. 112-113.
These figures show a hierarchical data line structure based on one bit line pair in each sub memory array.
Referring to FIG. 15, bit lines BLa and BLb are connected at nodes N3a and N3b to segment data line pair SI/Oa and SI/Ob through N channel MOS transistors T1a and T1b, and receiving at their gates a column signal Y, respectively. Segment data lines SI/Oa and SI/Ob are connected at nodes N4a and N4b to data lines of global data line pair GI/Oa and GI/Ob through N channel transistors T2a and T2b, respectively, the transistors receiving at their gates a sub memory array selecting signal BS. The global data line has one end connected to a Din buffer 73 through a write drive 71, so as to receive data input from an external terminal Din. Meanwhile, each of the nodes N5a and N5b of the global data line is connected to a main amplifier MA through a preamplifier PA, and provides data externally through an external terminal Dout. In this manner, in the hierarchical data line structure of FIG. 15, segment data lines and global data lines are provided by SI/O line pair and GI/O pair commonly used for reading/writing operations. The bit line and segment data line are switched by column decoder signal Y, while the segment data line and the global data line are switched by the control signal BS. However, in this structure, potential difference between the bit line pair is transferred through a transfer gate to the segment data line and the global data line. Therefore, the length of the data lines as a whole is long, and potential difference at the end of the global data lines is reduced, due to the additional capacitance of the data lines. Therefore, it takes much time to amplifier the data at the preamplifier PA.
FIG. 16 shows another conventional hierarchical data line structure.
Referring to the figure, the structure differs from the hierarchical data line structure shown in FIG. 15 in that the segment data lines for reading and writing are provided separately. More specifically, bit line pair BLa and BLb are connected at nodes N7a and N7b through N channel MOS transistors T5a and T5b, which receive at their gates a read column signal YW, and through a read amplifier RA, to segment data line pair SWBa and SWBb for writing.
Read amplifier RA includes N channel MOS transistors T3a and T4a connected in series between the ground potential and a node N6a of one segment data line SRBa of the pair for reading, and N channel MOS transistors T3b and T4b connected in series between the ground potential and a node N6b of the other segment data line SRBb of the pair for reading. One bit line BLa of the bit line pair is connected to the gate of transistors T3a, and the other bit line BLb of the bit line pair is connected to the gate of transistors T3b. A column signal YR for reading is input to the gates of transistors T4a and T4b.
Segment data line pair SRBa and SRBb for reading are connected at nodes N9a and N9b to global data lines GI/Oa and GI/Ob through N channel MOS transistors T7a and T7b, respectively, to the gates of which transistors the read control signal BSR is input. Segment data line pair SWBa and SWBb for writing are connected at nodes N8a and N8b to global data lines GI/Oa and GI/Ob through N channel MOS transistors T6a and T6b, to the gates of which transistors a write control signal BSW is input. Except these points, the structure is the same as that shown in FIG. 15.
In this hierarchical data line structure, the read data of the bit line pair is amplified by read amplifier RA and transmitted to segment data lines SRBa and SRBb for reading, while write data is written through segment data lines SWBa and SWBb for writing and transfer gates T5a and T5b, which are controlled by column signal YW for writing, to bit line pair BLa an BLb. The segment data line pair for reading and the global data line pair are switched by the read control signal BSR, while segment data line pair for writing and the global data line pair are switched by write control signal BSW. Increase in speed of data reading/writing operations in the hierarchical data line structure is discussed in 1990 Symposium on VLSI Circuit Digest of Technical Papers pp. 17-18.
However, the above described hierarchical data line structures are not sufficient to further increase the speed of operation of. semiconductor memory devices having ever increasing storage capacity, and the above described structures are not satisfactory also in view of the area occupied by the data pairs.